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SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 1 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 60 a vrpower ? smart power stage (sps) module with integrated high-accuracy current an d temperature monitors description the SIC645 is a smart vrpower ? device that integrates a high side and low side mosfet, a high performance driver with integrated bootstrap fe t. the SIC645 offers high accuracy current and temperature monitors that can be fed back to the controller and doubler to complete a multiphase dc/dc system. they simplify design and increase performance by eliminating the dcr sensing network and associated thermal compensation. light-load efficiency is supported via a dedicated left control pin. an industry leading thermally enhanced dual cooled, 5 mm x 5 mm powerpak ? mlp package allows minimal overall pcb real estate and low-profile construction. the devices feature a 3.3 v (SIC645a) or 5 v (SIC645) compatible tri-state pwm input that, working together with multiphase pwm controllers, w ill provide a robustsolution in the event of abnormal operating conditions. the SIC645 also improves system perfo rmance and reliability with integrated fault protection of uvlo, over-temperature and over-current. an open -drain fault reporting pin simplifies the handshake between the smart vrpower device and multiphase controllers and can be used to disable the controller during start-up and fault conditions. features ? input range: 4.5 v to 18 v ? supports 60 a dc current ? compatible with 3.3 v (SIC645a) and 5 v (SIC645) tri-state pwm ? down slope current sensing ? 3 % accuracy current monitor (imon) with ref in input ? 8 mv/c temperature monitor with ot flag ? dedicated low-side fet control input ? fault protection - high-side fet short and over-current protection - over-temperature protection - v cc and v in under voltage lockout (uvlo) ? open drain fault reporting output ? up to 2 mhz switching frequency ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? high frequency and high efficiency vrm and vrd ? core, graphic, and memory regulators for microprocessors ? high density vr for server, ne tworking, and cloud computing ? pol dc/dc converters and video gaming consoles typical application diagram fig. 1 - SIC645 typical application block diagram multipha s e controller pha s e boot +5 v en tmon s hoot- through protection s mart control v cc pv cc pv cc g nd v in +12 v g nd l out imon ref in c s #n c s rtn#n pwm pwm temp fault# l g ctrl c out v out s w v cc s ic645 g nd
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 2 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical application circuit with SIC645 fig. 2 - typical application circuit v cc v s env core r g ndv core v s a env core +3.3 v g nd addre ss v cc s env s a confi g v cc s v core p g v core v s env s a r g ndv s a v cc s c s rtnv s a c s v s a pwmv s a tempv s a s ic645 pwm imon ref in tmon l g ctrl s w v in v in v cc boot fault# 5 v pv cc g nd 5 v pha s e c s rtn1 c s 1 pwm1 tempvcore s ic645 pwm imon ref in tmon l g ctrl s w v in v in v cc boot fault# 5 v pv cc g nd 5 v pha s e c s rtn2 c s 2 pwm2 c s 3-5 c s rtn3-5 pwm3-5 c s rtn6 c s 6 pwm6 s ic645 pwm imon ref in tmon l g ctrl pha s e v in v in v cc boot fault# 5 v pv cc g nd 5 v s w pm s da npmalert pm s cl s vdata s vclk n s valert p g v s a nvrhot npinalert cfp v in s en v in n pha s e s s ic645 pwm imon ref in tmon l g ctrl s w v in v in v cc boot fault# 5 v pv cc g nd 5 v pha s e 5 v 5 v 5 v 5 v multipha s e controller
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 3 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 3 - typical application circuit v cc v s env core r g ndv core env core digital multipha s e +3.3 v v cc s v cc s load c s rtn1 c s 1 pwm1 tempv core c s 2-5 c s rtn2-5 pwm2-5 c s rtn6 c s 6 pwm6 n pha s e s pha s e doubler pwm pwmb c s enb c s ena c s rtna pwma c s rtnb 5 v s ic645 ref in tmon fault# imon l g ctrl s w v in v in v cc boot pwm 5 v pv cc g nd 5 v pha s e 5 v s ic645 ref in tmon fault# imon l g ctrl s w v in v in v cc boot pwm 5 v pv cc g nd 5 v pha s e pwm pwmb c s enb c s ena c s rtna pwma c s rtnb 5 v s ic645 ref in tmon fault# imon l g ctrl s w v in v in v cc boot pwm 5 v pv cc g nd 5 v pha s e i s l99227b ref in tmon fault# imon l g ctrl s w v in v in v cc boot pwm 5 v pv cc g nd 5 v pha s e 5 v v cc s pha s e doubler
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 4 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 functional block diagram fig. 4 - functional block diagram ordering information part number marking code temperature range (c) pwm input (v) package (rohs-compliant) SIC645adr-t1-ge3 45d -40 to +85 3.3 dual cooled powerpak mlp55-32l SIC645alr-t1-ge3 45l -10 to +100 3.3 dual cool ed powerpak mlp55-32l SIC645aer-t1-ge3 45e -40 to +125 3.3 dual cool ed powerpak mlp55-32l SIC645er-t1-ge3 45e -40 to +125 5 d ual cooled powerpak mlp55-32l boot v cc pv cc pv cc v in 20k pwm s w g nd nc pha s e l g ctrl fault# g l g h ot v ccpor 16.5k 33.5k (for 3.3 v) 2.5 v ldo hfet lfet v cc uvlo + - pha s e - + 100 mv g l or function v inpor v(t j ) v in uvlo + - 90 a + - och + - pwmh pwml v u g h v l g h och v ccpor v inpor h s driver l s driver a g nd -p g nd level s hifter tmon ot + - + - v(t j ) v(t max. ) temp. s en s e t j v(t j ) = 0.6 v + 8 mv x t j 2.5 v 2.5 v c s h g h_blank control dead time and s hoot-through logic v cc -boot level s hifter g l_blank control c s l ref in imon ref in +1.2 v och 1 s pul s e hfet s hort cal and level s hift pwm logic boot s witch control 16.5k (for 5.0 v)
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 5 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pinout configuration fig. 5 - SIC645 pinout configuration pin configuration pin number name function 1 lgctrl lower gate cont rol signal input. lo = gl lo (lfet off). hi = normal operation (gl and gh strictly obey pwm). this pin should be driven with a logic signal, or externally tied high if not required; it should not be left floating. 2v cc +5 v logic bias supply. place a high quality low esr ceramic capacitor (~1 f/x7r) in close proximity from this pin to gnd. 3pv cc +5 v gate drive bias supply. place a high quality low esr ceramic capacitor (~1 f/x7r) in close proximity from this pin to gnd. 4, 6, 7, 8, 17, 18, 19, 20, 29, 33, 35 gnd gnd pins are internally connected . pins 4 and 29 should be connect ed directly to the nearby gnd paddles on package bottom. fig. 15 shows gnd pa ddles should be connected to the system gnd plane with as many vias as possible to maximize thermal and electrical performance. 5 nc no connect (this is a low-side gate driver outp ut (gl), optional to moni tor for system debugging). 9, 10, 11, 12, 13, 14, 15, 16 sw switching junction node between hfet source and lfet drain. conne ct directly to output inductor. 21, 22, 23, 27, 34 v in input of power stage (to drain of hfet). place at least 2 ceramic capacitors (10 f or higher, x5r or x7r) in close proximity across v in and gnd. pin 27 should not be used for decoupling. for optimal performance, place as many vias as possible in the bottom side v in paddle. 24 phase return of boot capacitor. internal ly connected to sw node so no external routing required for sw connection. 25 boot floating bootstrap supply pi n for the upper gate drive. place a high quality low esr ceramic capacitor (0.1 f/x7r to 0.22 f/x7r)i n close proximity across boot and phase pins. 26 fault# open drain output pin. any fault (over-current, ov er-temperature, shorted hfet, or por / uvlo) will pull this pin to ground. this pin may be connected to the controller enable pin or used to signal a fault at the system level. 28 pwm pwm input of gate driver, compatible with 3.3 v and 5 v tri-state pwm signal. 30 ref in input for external reference voltage for imon signal . this voltage should be between 0.8 v and 1.6 v. connect ref in to the appropriate current sense input of the controller. place a high quality low esr ceramic capacitor (~ 0.1 f) in clos e proximity from this pin to gnd. 31 imon current monitor output , referenced to ref in . imon will be pull ed high (to ref in +1.2 v) to indicate an hfet shorted or over-current fault. connect the imon output to the appropriate current sense input of the controller. no more than 56 pf capacitance can be directly connected across imon and ref in pins. with a 100 ? series resistor, up to 470 pf may be used. 32 tmon temperature monitor output. for multiphase, the tmon pins can be connected together as a common bus; the highest voltage (representing the highest temperature) will be sent to the pwm controller. tmon will be pulled high (to 2.5 v) to indicate an over -temperature fault. no more than 250 pf total capacitance can be directly connected across tmon and gnd pins; with a series resistor, a higher capacitance load is allowed, such as 1 k ? for 100 nf load. 1 4 2 3 5 8 6 7 17 18 19 20 21 22 23 32 31 30 29 28 27 26 25 24 9101112 13 14 15 16 l g ctrl v cc pv cc g nd g l g nd g nd g nd g nd g nd g nd g nd v in v in v in s w s w s w s w s w s w s w s w imon ref in g nd pwm v in fault# boot pha s e tmon v in g nd g nd 33 34 35
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 6 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any ot her conditions beyond those indicated in the operational section s of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. notes a. ? ja is measured in free air with the component mounted on a high effective thermal conduc tivity test board with direct attach feat ures. b. for ? jc , the case temperature location is the center of the exposed metal pad on the package underside. c. these ratings vary with pcb layout and operating condition, and limited by device temperature and thermal shutdown trip point . absolute maximum ratings electrical parameter symbol conditons limit unit supply voltage v cc , pv cc -0.3 to +6 v input supply voltage v in -0.3 to +25 phase, sw voltage v ph-gnd , v sw-gnd gnd - 10 v, < 20 ns pulse width, 10 j -0.3 to +25 boot voltage v boot_gnd -0.3 to +36 other i/o pin voltage -0.3 to v cc + 0.3 maximum junction temperature (plastic package) 150 c maximum storage temperature range -65 to +150 lead (pb)-free reflow profile -- recommended operating range electrical parameter mi nimum typical maximum unit operating junction temp erature range -40 - 125 c supply voltage (v cc , pv cc ) - 5 5 % - v input supply voltage (v in )4.5-18 thermal information thermal resistance ? ja (c/w) ? jc (c/w) dual cooled powerpak mlp55-32l a, b, c 10.7 1.6
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 7 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical specifications (recommended operating conditions , unless otherwise noted. t j = -40 c to +125 c) parameter symbol test conditions limits unit min. a typ. max. a power rating maximum instant power dissipation t a = 25 c, 150 a b -100- w maximum continuous power dissipation t a = 25 c, ? ja = 10 c/w, t j = 150 c b - 12.5 - thermal resistance thermal resistance junction to pcb ? jb b -5.2- c/w thermal resistance junction to ambient ? ja 0 lfm b - 10.7 - 400 lfm b -9.3- v cc supply current logic standby current iv cc pwm = open - 4.75 - ma gate drive standby current ipv cc pwm = open - 100 - a logic operational current iv cc pwm = 300 khz - 4.75 - ma gate drive operat ional current ipv cc pwm = 300 khz - 15 - power-on reset and enable v cc rising por threshold - 3.86 4.20 c v v cc falling por threshold 3.20 c 3.58 - v cc por hysteresis -280-mv v cc por delay to operation - 125 197 c s v in rising por threshold - 4 4.2 c v v in falling por threshold 3.4 c 3.5 - v in por hysteresis -445-mv 3.3 v pwm input (see timing diagram) sink impedance - 33.5 - k ? source impedance - 16.5 - tri-state lower gate falling threshold v cc = 5 v -1.11- v tri-state lower gate rising threshold - 0.87 - tri-state upper gate ri sing threshold - 2.13 - tri-state upper gate falling threshold - 1.95 - tri-state shutdown window 1.3 c -1.8 c 5 v pwm input (see timing diagram) sink impedance - 16.5 - k ? source impedance - 16.5 - tri-state lower gate falling threshold v cc = 5 v -1.51- v tri-state lower gate rising threshold - 1.14 - tri-state upper gate ri sing threshold - 3.24 - tri-state upper gate falling threshold - 3.02 - tri-state shutdown window 1.6 c -2.8 c switching time gh turn-on propagation delay t pdhu gl low to gh high, see fig. 6 - 8 - ns gh turn-off propagation delay t pdlu pwm low to gh low, see fig. 6 - 40 - gl turn-on propagation delay t pdhl gh low to gl high, see fig. 6 - 8 - gl turn-off propagation delay t pdll pwm high to gl low, see fig. 6 - 23 - gl exit tri-state propagation delay t pdtsl tri-state to gl high), see fig. 6 - 25 - gh exit tri-state propagation delay t pdtsu tri-state to gh high, see fig. 6 - 35 - pwml tri-state shutdown hold-off time t tsshdl pwm low to gl low, see fig. 6 - 40 - pwmh tri-state shutdown hold-off time t tsshdu pwm low to gh low, see fig. 6 - 50 -
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 8 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. compliance to datasheet limits is assured by one or more methods: produc tion test, characteriza tion and/or design. b. these ratings vary with pcb layout and operating condition, and limited by sps temperature an d thermal shutdown trip point. c. limits apply across the operating temperature range. timing diagram fig. 6 - timing diagram current monitor iref in voltage range 0.8 c 1.2 1.6 c v imon current gain accuracy (v cc = 5 v) 10 a, t j = 90 c - 2 - % ? 10 a, t j = 40 c to 25 c - 3 - ? 10 a, t j = 20 c to 125 c - 4 - ? 10 a, t j = 0 c to 125 c - 5 - downslope blanking time -160-ns hfet over-c urrent trip -90-a imon to iref in at ocp 1.1 c 1.2 1.3 c v temperature monitor over-temperature rising threshold -140- c over-temperature falling threshold -125- over-temperature hysteresis -15- temperature coefficient t j = 25 c to 125 c - 8 - mv/k t j = -40 c to +25 c - 8 - tmon voltage at 25 c temperature v (t j ) = 0.6 v + (8 mv x t j ) - 0.80 - v tmon high at over-temperature 2.3 c 2.5 2.7 c fault pin output low voltage 5 ma - 0.18 0.26 v leakage current -16-na bootstrap diode forward voltage drop 5 ma - 0.09 - v on-resistance r f -16- ? lgctrl pin rising threshold logic high, (normal: obeys pwm) - 1.29 1.6 v falling threshold logic low, (forces gl low; left off) 0,70 c 1.01 - mosfets high-side mosfet (hfet) r ds(on) -3.6- m ? low-side mosfet (lfet) r ds(on) -0.76- electrical specifications (recommended operating conditions , unless otherwise noted. t j = -40 c to +125 c) parameter symbol test conditions limits unit min. a typ. max. a pwm g h g l t fl t pdhu t pdll t rl t t ss hdl t pdt s t pdt s u t fu t ru t pdlu t pdhl t ss hdu t pdlfur t pduflr
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 9 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (p vcc = 5 v, t a = 25 c, unless otherwise stated) fig. 7 - 1.8 v v out power stage efficiency (v in = 12 v, f sw = 500 khz; l out = 0.18 h/0.17m ? /fp1008-180-r; auto-phase enabled in 6-phase operation) fig. 8 - power stage efficiency (v in = 12 v, f sw = 500 khz; l out = 0.18 h/0.17m ? /fp1008-180-r fig. 9 - power dissipation (v in = 12 v, f sw = 500 khz; l out = 0.18 h/0.17m ? /fp1008-180-r fig. 10 - 1.2 v power stage efficiency (v in = 12 v, f sw = 500 khz; l out = 0.18 h/0.17m ? /fp1008-180-r; auto-phase enabled in 6-phase operation) fig. 11 - power stage efficiency (v in = 12 v, f sw = 500 khz; l out = 0.18 h/0.17m ? /fp1008-180-r fig. 12 - power dissipation (v in = 12 v, f sw = 500 khz; l out = 0.18 h/0.17m ? /fp1008-180-r 80 82 84 86 88 90 92 94 96 98 0 30 60 90 120 150 180 210 240 efficiency (%) load (a) exclude 5 v lo ss e s include 5 v lo ss e s 80 82 84 86 88 90 92 94 96 0 10 20 30 40 50 60 load (a) efficiency (%) 2.50 v 1.80 v 1.50 v 1.35 v 1.20 v 1.00 v 0.90 v 0.80 v 0 2 4 6 8 10 12 14 0 10 20 30 40 50 60 power lo ss e s (w) load (a) 2.50 v 1.80 v 1.50 v 1.35 v 1.20 v 1.00 v 0.90 v 0.80 v 80 82 84 86 88 90 92 94 96 98 0 30 60 90 120 150 180 210 240 efficiency (%) load (a) exclude 5 v lo ss e s include 5 v lo ss e s ss e s (w) load (a) 700 khz 800 khz 400 khz 500 khz 600 khz
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 10 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 detailed operational description the SIC645 is an optimized dr iver and power stage solution for high density synchronous dc/dc power conversion. it includes high performance gh and gl drivers, a nfet controlled to function as a bootstrap diode, and mosfet pair optimized for high swit ching frequency buck voltage regulators. it also includes advanced power management features. 1. accurate current and th ermal reporting outputs 2. fault protections of hfet over-current, hfet short, over-temperature, v cc uvlo, and v in uvlo power-on reset (por) during initial start-up, the v cc voltage rise is monitored. once the rising v cc voltage exceeds 3.86 v (typical) for 125 s, then normal operation of the driver is enabled. the pwm signals are passed throug h to the gate drivers, the tmon output is valid, and the imon output starts at zero, and becomes valid on the first gl signal. if v cc drops below the falling threshold of 3.58 v (typical), operation of the driver is disabled. the pv cc voltage is not monitored as it should to be from the same supply as v cc . v in por is also monitored. when both v cc and v in reach above their por trip points, it enables hfet over-current protection. both v cc and v in por are gated to the fault# pin, which goes high once both v cc and v in are above their por levels and no other faults occur. shoot-through protection prior to por, the undervoltage protection function is activated and both gh and gl are held active low (hfet and lfet off). after por (the ri sing thresholds; see electrical specifications), and 125 s delay, the pwm and lgctrl signals are used to control both high-side and low-side mosfets, as shown in table 1. SIC645s dead time control is optimized for high efficiency and guarantees that simultaneous conduction of both fets cannot occur. should the driver have no bi as voltage applied (either v cc or pv cc missing) and be unable to actively hold the mosfets off, an integrated 20 k ? resistor from the upper mosfet gate to source will aid in keeping the hfet device in its off state. this can be especially critical in applications where the input voltage rises prior to the SIC645 v cc and pv cc supplies. tri-state pwm input the SIC645a supports a 3.3 v pwm tri-level input, compatible with vishays digi tal multiphase controllers as well as other control ics utilizing 3.3 v pwm logic. use the SIC645 for 5 v pwm logic. shou ld the pin be pulled into and remain in the tri-state window for a set hold off time ( ? 25 ns), the driver will force both mosfets to their off states. when the pwm signal moves outside the shutdown window, the driver immediately resumes driving the mosfets according to the pwm commands. this feature is utilized by vishay pwm controllers as a method of forcing both mo sfets off. should the pwm input be left floating, the pin will be pulled into the tri-state window internally and thus forc e both mosfets to a safe off state. although the pwm input can sustain a voltage as high as v cc , the SIC645 is not compatible with a controller that actively drives its mid-level in tri-state higher than 1.7 v. bootstrap function the SIC645 features an internal nfet that is controlled to function as a bootstrap diod e. a high quality ceramic capacitor should be placed in close proximity across the boot and phase pins. the bootstrap capacitor can range between 0.1 f to 0.22 f (0402 to 0603 and x5r to x7r) for normal buck swit ching applications. current monitoring lfet current is monitored and a signal proportional to that current is output on the imon pin (relative to the ref in pin). the imon and ref in pins should be connected to the appropriate current sense input pin of the controller. this method does not require external r sense or dcr sensing of inductor current. fig. 13 depicts the low-side current sense concept and demonstrates how the accuracy will be defined. after the falling edge of pwm, there are two delays; one that represents the expected propagation delay from pwm to gh/sw, and a second blanking delay to allow time for the transition to settle; typical to tal time is ~ 350 ns. the imon output approximates the actual i l waveform shown within the tolerance band. fig. 13 - lfet curre nt sample diagram table 1 - gh and gl operation truth table pwm lgctrl gh gl hfet, lfet comment tri-state x 0 0 both off - 0101lfet onnormal 1 1 1 0 hfet on normal 0 0 0 0 lfet off gl low 1 0 1 0 hfet on normal on dly off dly s w g l g h pwm i l x imon g ain tolerance band imon
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 11 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 the hfet current is not monito red in the same way, so no valid measured current is ava ilable while pwm is high (and the short delays befo re and after). during this time, the imon will output the last va lid lfet current before the sampling stopped. on start-up after por, the imon will output zero (relative to ref in , which represents zero current) until the switching begins, and then the current can be properly measured. the high-side fet current is separately monitored for oc conditions; see the over-cu rrent protection section. over-current protection fig. 14 shows the timing diag ram of an over-current fault. there is a comparator monitoring the hfet current while it is on (gh high; also requires v in por above its trip point). if the current is higher than 90 a (typical; not user-programmable), then an oc fault is detected. the gh will be forced low, even if pwm is still high; this effectively shortens the pwm (and gh) pulse width, to limit the current. the imon pin is pulled up to ref in +1.2 v, which will be detected by the controller as an over-current fault. the controller is then expected to force pwm to tri-state (which gates off both fets) or low stat e (turns on lfet), either of which signals the sps that the fault has been acknowledged. this starts a ~ 1 s fault clear delay. the imon flag is released after the delay. the driver will then respond to pwm inputs normally. note that if the controller does not acknowledge, the imon flag will stay high indefinitely, which will also hold gh low. if oc is detected, the fault# pin is also pulled low; the timing on the fault# pin will follow that of the imon pin. fig. 14 - over-current fault timing diagram shorted hfet protection in the case of a shorted hfet, the sw node will have excessive positive voltage present even when the lfet is turned on. the SIC645 monitors the sw node during periods when the lfet is on (gl is high), and should that voltage exceed 100 mv (typical), the hfet short fault is declared. the SIC645 will pull the imon pin high, and the fault# will be pulled low. but the fa ult will be latched; v cc por is needed to reset it. gh will be gated low (ignore pwm = high), but the SIC645 will still respond to pwm tri-state and logic low. thermal monitoring the SIC645 monitors its intern al temperature and provides a signal proportional to that temperature on the tmon pin. tmon has a voltage of 600 mv at 0 c and reflects temperature at 8 mv/c. the tmon output is valid 125 s after v cc por. fig. 15 - over-temperature fault fig. 15 shows a simplified funct ional representation. the top section includes the sensor and the output buffer. the bottom section includes the protection sensing, that will pull the output high. the tmon pin is configured internally such that a user can tie multiple pins together externally and the resulting tmon bus will assume the voltage of the highest contributor (representing the highest temperature). thermal protection if the internal te mperature exceeds th e over-temperature trip point (+140 c typical), the tmon pin is pulled high (to ~2.5 v), and the fault# pin is pulled low. no other action is taken on-chip. both the tmon and fault# pins will remain in the fault mode, until the j unction temperature drops below +125 c typical; at that point, the tmon and fault# pins resume normal operation; the dmp can detect that the fault condition has gone away, and decide what to do next. fault reporting over-current and shorted hfet detections will pull the imon pin to a high (fault) le vel, such that the dmp should quickly recognize it as out of the normal range. over-temperature dete ction will pull the tmon pin to a high (fault) level, such that the pwm controller should quickly recognize it as out of the normal range. all of the above faults, plus the v cc and v in por (uvlo) conditions, will also pull down the fault# pin. this can be used by the controller (or system) as fault detection, and can also be used to disable the co ntroller, through its enable pin. the fault reporting and re spective sps response are summarized in table 2. ilim 0 hfet ? current pwm g h g l fault clear delay 1 ? s imon - refin 1.2 v re s ume normal op (if recover s ) ? ? ? followpwm low to s upport ov following oc no g h allowed fault# dmp enter s pwm mid- s tate or low to acknowledge fault 600 mv + 8 mv/c x temperature tmon pin fault reporting configuration over-temperature
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 12 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout considerations proper pcb layout will reduce noise coupling to other circuits, improve thermal perf ormance, and maximize the efficiency. the following is meant to lead to an optimized layout: ? place multiple 10 f or greater ceramic capacitors directly at device between v in and p gnd as indicated in fig. 16 this is the most critical de coupling and reduced parasitic inductance in the power switching loop. this will reduce overall electrical stress on the device as well as reduce coupling to other circuits. best practice is to place the decoupling capacitors on the same pcb side as the device. for a design with tight space requirements, these decoupling capacitors can be placed under the device, i.e., bottom layer, as shown in fig. 18 ? connect gnd to the system gnd plane with a large via array as close to the gnd pins as design rules allow. this improves thermal and el ectrical performance. ?place pv cc , v cc and boot-phase decoupling capacitors at the ic pins as shown in fig. 16. ? note that the sw plane connecting the SIC645 and inductor must carry full load current and will create resistive loss if not sized properly. however, it is also a very noisy node that should not be oversized or routed close to any sensitive signals. best practice is to place the inductor as close to the device as possible and thus minimizing the required area for the sw connection. if one must choose a long route of either the v out side of the inductor or the sw side, choose the quiet v out side. best practice is to locate the SIC645 as close to the final load as possible and thus avoid noisy or lossy routes to the load. ? the imon and iref network an d their vias should not sit on the top of the v in plane, a keep out area is recommended, as shown in fig. 18. ? the pcb is the best thermal he atsink material than any top side cooling materials. the pcb always has enough vias to connect v in and gnd planes. insufficient vias will yield lower efficiency and very poor thermal performance. fig. 17 and fig. 18 show a mu ltiphase pcb layout example. table 2 - fault reporting summary fault event imon tmon fault# response oc high n/a low gh gated off. the controller should acknowledge and force its pwm to tri-state to keep both hfet and lfet off. the fault is cleared ? 1 s after pwm enters tri-state, otherwise, it stays asserted. (if system ovp occurs, the controller may sen pwm to turn on left) shorted hfet imon latched high n/a fault# latched low gh gated off, until faul t latch is cleared by v cc por. gl follows pwm. ot n/a high low gh and gl follow pwm. v cc uvlo imon - ref in = 0 v tmon not valid low switching stops while in uvlo. once above v cc por after 125 s: gh and gl follow pwm; the fault# is released; tmon is valid; imon - ref in is valid after gl first goes low. v in uvlo oc not valid n/a low gh and gl follow pwm.
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 13 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout for minimizing current loops fig. 16 - single-phase pcb layout for mini mizing current loops fig. 17 - multi-phase pcb layout example top layer 1 2 3 5 24 l g ctrl v cc +5 v pv cc g nd nc g nd g nd d n imon ref in g nd pwm v in fault# boot pha s e tmon 4 v in v in v in g nd(33) g n g n nd d g n nd d inductor s w s w s w s w s w s w s w s w 9 10 11 12 13 14 15 16 8 6 7 21 22 23 27 g nd g nd g nd 17 20 19 18 g nd (35) v in (34) g nd 25 24 26 28 29 30 31 32
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 14 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 18 - multi-phase pcb layout example bottom layer package outline drawing dual cooled powerpak mlp55-32l v in decoupling capacitor s keep out area s ide view top view detail "x" bottom view pin 1 index area d 2x 0.10 ca a b e q1 q2 p2 p1 s ee detail x a a1 a2 0.08 c c (nd4-1) x e ref. d2-2 0.2 d2-1 0.2 32 a m 0.10 c b 4 1 b e2-1 e2-2 k1 k2 (nd1-1) x e ref. 8 (nd2-1) x e ref. 9 16 d2-3 l l1 l (nd3) x e ref. e e2-3 23 l 24 17 9 0.2 ref. 0.00 min. 0.05 max. c typical recommended land pattern (4.80) (4.00) (0.40) (2.00) (1.50) (2 x 1.15) (0.40) (1.85) (0.70) (27 x 0.50) (3 x 3.50) (4.80) (3.00) (32 x 0.25) (22 x 0.60) pin 1 index area 5 5
SIC645 www.vishay.com vishay siliconix s16-2233-rev. b, 31-oct-16 15 document number: 65424 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes (1) use millimeters as the primary measurement. (2) dimensioning and to lerances conform to asme y14.5m-1994. (3) n is the number of terminals. nd1 and nd3 is the number of terminals in y-direction and nd2 and nd4 is the number of terminals in x-direction. (4) dimension b applies to plated terminal and is measured betwee n 0.20 mm and 0.25 mm from terminal trip. (5) the configuration of the pin #1 identifier is optimal, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. (6) exact shape and size of this feature is optional. (7) package warpage max 0.08 mm. (8) applied only for terminals. (9) tiebar shown (if present) is a non-functional feature. vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65424 . dim. millimeters min. nom. max. a (8) 0.56 0.61 0.66 a1 0.00 - 0.05 a2 0.20 ref. b (4) 0.20 0.25 0.30 d 5.00 bsc d2-1 1.45 1.50 1.55 d2-2 1.95 2.00 2.05 d2-3 4.25 4.30 4.35 e 0.50 bsc e 5.00 bsc e2-1 1.10 1.15 1.20 e2-2 1.80 1.85 1.90 e2-3 1.10 1.15 1.20 k1 0.55 bsc k2 0.15 bsc l 0.35 0.40 0.45 l1 0.25 0.30 0.35 p1 3.95 4.00 4.05 p2 0.75 - 1.15 q 1 2.05 2.10 2.15 q 2 1.30 1.35 1.40 n (3) 32 nd1 (3) 8 (pin 1 to pin 8) nd2 (3) 8 (pin 9 to pin 16) nd3 (3) 7 (pin 17 to pin 23) nd4 (3) 9 (pin 24 to pin 32)
package information www.vishay.com vishay siliconix revision: 24-oct-16 1 document number: 77713 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 powerpak ? mlp55-32 double cooling case outline notes ? use millimeters as the primary measurement. ? dimensioning and tolerances conform to asme y14.5m-1994. ? the pin 1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package b ody. ? exact shape and size of this feature is optional ? package warpage max. 0.08 mm. (1) n is the number of terminal s. nd1 and nd3 is the number of te rminals in each y-direction. nd2 and nd4 is the number of terminal s in each x-direction. (2) dimensions b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. (3) applied only for terminals. dim. millimeters inches min. nom. max. min. nom. max. a (3) 0.56 0.61 0.66 0.022 0.024 0.026 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (2) 0.20 0.25 0.30 0.078 0.098 0.011 d 5.00 bsc 0.196 bsc d2-1 1.45 1.50 1.55 0.057 0.059 0.061 d2-2 1.95 2.00 2.05 0.077 0.079 0.081 d2-3 4.25 4.30 4.35 0.167 0.169 0.171 e 0.50 bsc 0.020 bsc e 5.00 bsc 0.197 bsc e2-1 1.10 1.15 1.20 0.043 0.045 0.047 e2-2 1.80 1.85 1.90 0.071 0.073 0.075 e2-3 1.10 1.15 1.20 0.043 0.045 0.047 k1 0.55 bsc 0.022 bsc k2 0.15 bsc 0.006 bsc l 0.35 0.40 0.45 0.014 0.016 0.018 l1 0.25 0.30 0.35 0.010 0.012 0.014 p1 3.95 4.00 4.05 0.1555 0.1575 0.1595 p2 0.75 - 1.15 0.030 - 0.045 o1 2.05 2.10 2.15 0.046 0.048 0.050 o2 1.30 1.35 1.40 0.049 0.051 0.053 n (1) 31 31 nd1 (1) 8 (pin 1 to pin 8) 8 (pin 1 to pin 8) nd2 (1) 8 (pin 9 to pin 15) 8 (pin 9 to pin 15) nd3 (1) 7 (pin 16 to pin 22) 7 (pin 16 to pin 22) nd4 (1) 9 (pin 23 to pin 31) 9 (pin 23 to pin 31) ecn: t16-0611-rev. a, 24-oct-16 dwg: 6054 a d e pin 1 dot by marking b a 0.10 c a 2 x mlp55-32l (5 mm x 5 mm) top view a1 a2 0.08 c c s ide view 8 32 16 9 1 23 17 24 p1 q1 q2 k1 k2 e2-1 e2-2 e2-3 0.2 0.2 d2-1 d2-2 d2-3 l l l1 e (nd1-1) x e ref. (nd3) x e ref. (nd4-1) x e ref. (nd2-1) x e ref. l b 0.10 cab 4 bottom view p2
pad pattern www.vishay.com vishay siliconix revision: 20-sep-16 1 document number: 77768 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended land pattern powerpak ? mlp55-32l all dimensions are in millimeters (d2-1) 1.50 (e2-1) 1.15 (e2-2) 1.85 0.40 (k3) 2.30 (e2-3) 1.15 (k2) 0.20 (p2) 1.70 (k1) 0.20 (p3) 0.55 (p1) 0.55 (b) 0.25 (l) 0.40 5.00 5.00 0.75 0.30 5.00 0.325 0.175 0.80 0.75 0.75 0.30 1.25 1.45 0.30 0.5 x 7= 3.50 0.75 0.30 1.60 0.30 0.50 0.75 0.30 0.5 x 3 = 1.50 1.00 0.5 x 2 = 1.00 (d2-2) 2.00 (d2-3) 4.50 0.40 1.35 (k4) 0.75 0.40 0.40 0.40 2.15 0.5 x 4 = 2.00 0.75 0.30 0.30 3.10 0.50 1.25 0.20 0.20 0.50 0.5 x 2 = 1.00 0.5 x 8 = 4.00 0.30 1.95 component for mlp55- 3 2l top si d e transparent view (no bottom view) lan d pattern for mlp55- 3 2l land pattern for mlp55-32l component for mlp55-32l 8 32 16 9 1 23 17 24 8 32 16 9 1 23 17 24 8 32 16 9 1 23 17 24 component an d lan d pattern for mlp55- 3 2l
legal disclaimer notice www.vishay.com vishay revision: 13-jun-16 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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